Computer Organizations- Question Paper- 4

Topics: Peripheral Devices & I/O Interface

Part A –MCQs (with Answers)

A peripheral device is a device that is:
A. Part of CPU
B. Connected externally to the computer
C. Inside ALU
D. Part of cache
Answer: B
Which of the following is an input device?
A. Printer
B. Monitor
C. Keyboard
D. Plotter
Answer: C
Which device is used for hard copy output?
A. Scanner
B. Printer
C. Mouse
D. MICR
Answer: B
A scanner is a:
A. Processing device
B. Input device
C. Output device
D. Storage device
Answer: B
Plotter is mainly used for:
A. Audio output
B. Video editing
C. Large drawings
D. Typing
Answer: C
Which is a pointing device?
A. Mouse
B. Printer
C. Speaker
D. RAM
Answer: A
MICR is used in:
A. Hospitals
B. Banks
C. Schools
D. Homes
Answer: B
OCR stands for:
A. Optical Code Reader
B. Optical Character Recognition
C. Output Character Reader
D. Online Code Recognition
Answer: B
I/O stands for:
A. Input/Output
B. Internal/Outer
C. Input/Outer
D. Interface Output
Answer: A
The I/O interface connects:
A. CPU and memory
B. CPU and peripherals
C. RAM and ROM
D. ALU and CU
Answer: B
Which is an output device?
A. Keyboard
B. Mouse
C. Monitor
D. Scanner
Answer: C
Joystick is mainly used for:
A. Printing
B. Gaming
C. Scanning
D. Storage
Answer: B
Touch screen is:
A. Only input
B. Only output
C. Both input and output
D. Storage
Answer: C
Speaker is a:
A. Input device
B. Output device
C. Storage device
D. Interface
Answer: B
Which is a storage peripheral?
A. Hard disk
B. Mouse
C. Keyboard
D. Plotter
Answer: A
USB is a type of:
A. CPU
B. Interface
C. Software
D. Memory
Answer: B
Full form of USB:
A. Universal Serial Bus
B. Unique System Bus
C. Universal System Base
D. User Serial Bus
Answer: A
Which transfer method sends one bit at a time?
A. Parallel
B. Serial
C. Block
D. Direct
Answer: B
Which transfer sends multiple bits at once?
A. Serial
B. Parallel
C. Single
D. Simplex
Answer: B
Programmed I/O is also called:
A. Polling
B. DMA
C. Interrupt
D. Cache I/O
Answer: A
Interrupt driven I/O reduces:
A. Memory
B. CPU idle time
C. Disk size
D. Cache speed
Answer: B
DMA stands for:
A. Direct Memory Access
B. Data Memory Access
C. Direct Module Access
D. Disk Memory Access
Answer: A
DMA transfers data between:
A. CPU and ALU
B. Memory and I/O device
C. Cache and register
D. CU and RAM
Answer: B
Which signal indicates device needs attention?
A. Interrupt
B. Clock
C. Reset
D. Halt
Answer: A
I/O ports are used to:
A. Store programs
B. Connect peripherals
C. Increase speed
D. Compile code
Answer: B
Memory-mapped I/O uses:
A. Separate address space
B. Same address space as memory
C. Cache only
D. Register only
Answer: B
Isolated I/O uses:
A. Same address space
B. Separate address space
C. Cache space
D. Virtual space
Answer: B
Handshaking is used for:
A. Error
B. Synchronization
C. Storage
D. Coding
Answer: B
Buffer is used to:
A. Delete data
B. Temporarily store data
C. Print data
D. Scan data
Answer: B
Which is NOT an input device?
A. Keyboard
B. Mouse
C. Monitor
D. Scanner
Answer: C
Which is NOT an output device?
A. Printer
B. Plotter
C. Speaker
D. Trackball
Answer: D
Trackball is a:
A. Output device
B. Pointing input device
C. Storage device
D. Display
Answer: B
Light pen works with:
A. Paper
B. Monitor screen
C. CPU
D. Printer
Answer: B
Barcode reader is used for:
A. Audio
B. Code scanning
C. Printing
D. Gaming
Answer: B
Which method gives highest I/O speed?
A. Programmed I/O
B. Interrupt I/O
C. DMA
D. Polling
Answer: C
I/O controller is also called:
A. Interface
B. Compiler
C. Loader
D. Editor
Answer: A
Port-mapped I/O is another name for:
A. Memory mapped I/O
B. Isolated I/O
C. DMA
D. Cache I/O
Answer: B
Which device converts hard copy to soft copy?
A. Printer
B. Scanner
C. Plotter
D. Speaker
Answer: B
Which is used for video input?
A. Webcam
B. Printer
C. Speaker
D. Plotter
Answer: A
Interface logic helps in:
A. Compilation
B. Speed matching
C. Gaming
D. Typing
Answer: B
Data register in I/O interface stores:
A. Address
B. Data
C. Program
D. Cache
Answer: B
Status register stores:
A. Device status
B. Program
C. Data
D. Instruction
Answer: A
Control register stores:
A. Commands
B. Output
C. Input
D. Cache
Answer: A
Daisy chaining is used in:
A. Interrupt priority
B. Printing
C. Storage
D. Coding
Answer: A
Priority interrupt is needed when:
A. Many devices request service
B. No device works
C. CPU fails
D. Memory fails
Answer: A
Simplex mode means:
A. One-way communication
B. Two-way
C. Both-way simultaneous
D. Random
Answer: A
Half duplex means:
A. One-way
B. Two-way but not simultaneous
C. Simultaneous both ways
D. No transfer
Answer: B
Full duplex means:
A. One-way
B. Alternate-way
C. Simultaneous both ways
D. Slow-way
Answer: C
Which is NOT an I/O transfer technique?
A. DMA
B. Interrupt
C. Polling
D. Paging
Answer: D
I/O interface reduces:
A. Device mismatch problem
B. CPU speed
C. Memory size
D. Disk size
Answer: A

Part B –Fill in the Blanks (with Answers)

Peripheral devices are connected ______ to the computer.
Answer: externally
Keyboard is an ______ device.
Answer: input
Printer is an ______ device.
Answer: output
Scanner converts hard copy into ______ copy.
Answer: soft
MICR is mainly used in ______.
Answer: banks
OCR stands for Optical Character ______.
Answer: Recognition
USB stands for Universal ______ Bus.
Answer: Serial
I/O means Input and ______.
Answer: Output
I/O interface connects CPU with ______ devices.
Answer: peripheral
Serial transmission sends ______ bit at a time.
Answer: one
Parallel transmission sends ______ bits at a time.
Answer: multiple
Programmed I/O is also called ______.
Answer: polling
DMA stands for Direct ______ Access.
Answer: Memory
Interrupt driven I/O reduces CPU ______ time.
Answer: idle
Buffer is used for ______ storage.
Answer: temporary
Memory-mapped I/O shares address space with ______.
Answer: memory
Isolated I/O uses ______ address space.
Answer: separate
Handshaking provides ______ between device and CPU.
Answer: synchronization
Mouse is a ______ device.
Answer: pointing
Plotter is used for large ______.
Answer: drawings
Speaker produces ______ output.
Answer: audio
Monitor produces ______ output.
Answer: visual
Webcam is a ______ device.
Answer: input
Light pen works on ______ screen.
Answer: monitor
Trackball is similar to a ______.
Answer: mouse
Barcode reader reads ______ codes.
Answer: bar
Control register stores ______.
Answer: commands
Status register stores device ______.
Answer: status
Data register stores ______.
Answer: data
Daisy chaining is used for interrupt ______.
Answer: priority
Full duplex allows ______ communication.
Answer: simultaneous
Half duplex allows two-way but not ______ communication.
Answer: simultaneous
Simplex allows ______ way communication.
Answer: one
DMA transfers data without CPU ______.
Answer: intervention
I/O controller is also called ______.
Answer: interface
USB is a ______ interface.
Answer: serial
Interrupt is a ______ signal.
Answer: hardware
Polling checks device ______.
Answer: status
Interface resolves speed ______ problem.
Answer: mismatch
Hard disk is a ______ device.
Answer: storage
Touch screen is both ______ and output.
Answer: input
Printer produces ______ copy.
Answer: hard
Scanner produces ______ copy.
Answer: soft
Joystick is used in ______.
Answer: games
Port-mapped I/O is also called ______ I/O.
Answer: isolated
Memory-mapped I/O uses ______ instructions.
Answer: memory
I/O port is used to connect ______.
Answer: devices
DMA gives ______ speed data transfer.
Answer: high
Interrupt improves CPU ______.
Answer: efficiency
Peripheral devices are also called ______ devices.
Answer: external

==================================================================

TOPICS:- Asynchronous Data Transfer / Modes / Priority Interrupt

PART 1 —MCQs (with Answers)

🔹 Asynchronous Data Transfer / Modes / Priority Interrupt — MCQs

Asynchronous data transfer uses ______ signal for coordination.
A) Clock
B) Handshaking
C) Counter
D) Register
Answer: B
Asynchronous transfer does not require:
A) Control signal
B) Clock signal
C) Acknowledge signal
D) Request signal
Answer: B
Handshaking involves how many control signals?
A) One
B) Two
C) Three
D) Four
Answer: B
The two handshaking signals are:
A) Start–Stop
B) Enable–Disable
C) Request–Acknowledge
D) Send–Receive
Answer: C
Strobe control method uses:
A) Two signals
B) Clock pulses
C) Single control signal
D) No control signal
Answer: C
In source-initiated strobe, strobe is generated by:
A) Receiver
B) Source
C) Memory
D) Bus
Answer: B
In destination-initiated strobe, strobe is generated by:
A) Source
B) Receiver
C) CPU
D) DMA
Answer: B
Asynchronous transfer is used when devices have:
A) Same speed
B) Fixed timing
C) Different speeds
D) Same clock
Answer: C
Which is more reliable?
A) Strobe
B) Handshaking
C) Clocking
D) Polling
Answer: B
Data transfer without timing reference is called:
A) Synchronous
B) Asynchronous
C) Serial
D) Parallel
Answer: B

🔹 Modes of Data Transfer

Which is NOT a mode of data transfer?
A) Programmed I/O
B) Interrupt I/O
C) DMA
D) Cache I/O
Answer: D
Programmed I/O is also called:
A) Interrupt driven
B) Polling
C) DMA
D) Vector I/O
Answer: B
In Programmed I/O, CPU checks device status by:
A) Interrupt
B) Polling
C) DMA
D) Bus request
Answer: B
Interrupt-driven I/O reduces:
A) Memory
B) CPU idle time
C) Bus width
D) Register size
Answer: B
DMA stands for:
A) Direct Memory Access
B) Data Memory Allocation
C) Direct Module Access
D) Dynamic Memory Access
Answer: A
DMA transfers data between:
A) CPU and ALU
B) I/O and Memory
C) Register and Cache
D) CPU and Cache
Answer: B
DMA controller needs:
A) Interrupt
B) Bus control
C) Stack
D) Cache
Answer: B
Fastest data transfer mode is:
A) Programmed I/O
B) Interrupt I/O
C) DMA
D) Manual I/O
Answer: C
Programmed I/O wastes:
A) Disk space
B) CPU time
C) Cache
D) Registers
Answer: B
Interrupt I/O uses:
A) Polling
B) Signals
C) Interrupt request
D) Cache
Answer: C

🔹 Priority Interrupt

Priority interrupt decides:
A) Memory size
B) Instruction order
C) Which interrupt to serve first
D) Bus width
Answer: C
Priority encoder is used in:
A) ALU
B) Interrupt system
C) Cache
D) Register file
Answer: B
Daisy chaining is used for:
A) Memory control
B) Interrupt priority
C) DMA
D) Bus speed
Answer: B
Fixed priority means:
A) Changing order
B) Random order
C) Predefined order
D) No order
Answer: C
In daisy chain, priority is given based on:
A) Distance
B) Position
C) Speed
D) Voltage
Answer: B
Vectored interrupt provides:
A) Data value
B) Address of ISR
C) Clock
D) Bus signal
Answer: B
Non-vectored interrupt provides:
A) ISR address internally
B) ISR address externally
C) No ISR
D) DMA
Answer: B
Interrupt request line is called:
A) INTR
B) CLK
C) MAR
D) PC
Answer: A
Interrupt acknowledge signal is:
A) INTA
B) ACK
C) BUSY
D) READY
Answer: A
Priority resolver hardware is used when:
A) Multiple interrupts occur
B) One device exists
C) No interrupt
D) DMA active
Answer: A

🔹 Mixed Concept MCQs

Handshaking prevents:
A) Overflow
B) Data loss
C) Cache miss
D) Page fault
Answer: B
DMA bypasses:
A) Memory
B) CPU
C) Register
D) Cache
Answer: B
Interrupt improves:
A) CPU utilization
B) Memory size
C) Bus width
D) Instruction length
Answer: A
Polling checks device using:
A) Loop
B) Stack
C) Interrupt
D) DMA
Answer: A
Strobe method risk is:
A) Data mismatch
B) Timing problem
C) Overflow
D) Bus error
Answer: B
DMA needs bus grant from:
A) I/O device
B) CPU
C) Register
D) Cache
Answer: B
Interrupt service routine is stored in:
A) Disk
B) Memory
C) Cache
D) Register
Answer: B
ISR stands for:
A) Interrupt Service Routine
B) Internal System Register
C) Input Service Routine
D) Interrupt Stack Register
Answer: A
Priority encoder output is:
A) Binary code
B) Decimal code
C) Gray code
D) ASCII
Answer: A
Daisy chain disadvantage:
A) Slow response
B) Expensive
C) Large memory
D) Complex code
Answer: A
Asynchronous transfer is mostly used in:
A) I/O devices
B) Cache
C) ALU
D) Register
Answer: A
Handshaking is also called:
A) Two-line control
B) Clocking
C) Polling
D) DMA
Answer: A
Interrupt vector table stores:
A) Data
B) ISR addresses
C) Registers
D) Flags
Answer: B
Multiple interrupts are handled by:
A) Encoder
B) Decoder
C) Multiplexer
D) Counter
Answer: A
Programmed I/O is suitable for:
A) Slow devices
B) Fast transfer
C) DMA
D) Cache
Answer: A
DMA controller contains:
A) Address register
B) Counter
C) Control logic
D) All of these
Answer: D
Interrupt driven I/O uses:
A) Flags
B) Signals
C) ISR
D) All
Answer: D
Ready line is used in:
A) Asynchronous transfer
B) Cache
C) ALU
D) Register
Answer: A
Bus request in DMA is:
A) BR
B) BG
C) INT
D) ACK
Answer: A
Bus grant signal is:
A) BG
B) BR
C) ACK
D) INTR
Answer: A

PART 2 —Fill in the Blanks (with Answers)

Asynchronous transfer does not use a ______ signal.
Answer: clock
Handshaking uses ______ and acknowledge signals.
Answer: request
Strobe method uses ______ control signal.
Answer: single
Data transfer between unequal speed devices is called ______ transfer.
Answer: asynchronous
Programmed I/O is also called ______.
Answer: polling
DMA means ______ Memory Access.
Answer: Direct
Fastest I/O transfer mode is ______.
Answer: DMA
Interrupt driven I/O reduces ______ waiting time.
Answer: CPU
ISR stands for ______.
Answer: Interrupt Service Routine
Priority interrupt decides ______ order.
Answer: service
Daisy chaining provides ______ priority.
Answer: fixed
Priority encoder converts to ______ code.
Answer: binary
Interrupt request line is ______.
Answer: INTR
Interrupt acknowledge is ______.
Answer: INTA
DMA bypasses the ______.
Answer: CPU
Handshaking is more ______ than strobe.
Answer: reliable
Polling repeatedly checks device ______.
Answer: status
DMA needs ______ control.
Answer: bus
Vector interrupt supplies ______ of ISR.
Answer: address
Non-vectored interrupt does not supply ISR ______.
Answer: address
Multiple interrupts need ______ resolver.
Answer: priority
In daisy chain, nearest device has ______ priority.
Answer: highest
Interrupt improves CPU ______.
Answer: utilization
Strobe has ______ problem risk.
Answer: timing
DMA controller has address and ______ registers.
Answer: count
Handshaking uses ______ signals.
Answer: two
Programmed I/O wastes ______ cycles.
Answer: CPU
Interrupt is a ______ signal.
Answer: hardware
Asynchronous transfer uses ______ control.
Answer: independent
Bus request signal is ______.
Answer: BR
Bus grant signal is ______.
Answer: BG
Interrupt vector table is stored in ______.
Answer: memory
Priority interrupts avoid ______ conflict.
Answer: service
DMA transfer is ______ speed.
Answer: high
Polling uses a ______ loop.
Answer: checking
Handshaking prevents data ______.
Answer: loss
Interrupt driven I/O uses ______ routine.
Answer: service
Priority hardware uses ______ encoder.
Answer: priority
Asynchronous transfer is common in ______ devices.
Answer: I/O
Source initiated strobe is generated by ______.
Answer: sender
Destination initiated strobe is generated by ______.
Answer: receiver
Interrupt is generated by ______ device.
Answer: I/O
DMA needs bus ______.
Answer: grant
Programmed I/O is ______ method.
Answer: simple
Handshaking confirms data ______.
Answer: reception
Daisy chain is ______ priority scheme.
Answer: serial
Interrupt request is also called ______.
Answer: IRQ
DMA improves transfer ______.
Answer: speed
Interrupt saves CPU from ______ waiting.
Answer: busy
Asynchronous transfer uses ______ coordination.
Answer: signal

================================================================

TOPICS :- Numerical on Data Transfer Modes

Problem 1 — Programmed I/O Transfer Time

A device transfers 1 word = 4 bytes.
CPU polling time per word = 8 µs.
Total words to transfer = 2000.

Find total transfer time.

Solution:

Time per word = 8 µs
Words = 2000

Total time = 2000 × 8 µs
= 16000 µs = 16 ms

Answer: 16 ms

Problem 2 — DMA Transfer Time

DMA transfer rate = 20 MB/s
Data size = 5 MB

Find transfer time.

Solution:

Time = Data / Rate
= 5 / 20 sec
= 0.25 sec

Answer: 0.25 sec

Problem 3 — Interrupt I/O Overhead

Device generates interrupt every 500 µs.
ISR execution time = 50 µs.
Find CPU overhead percentage.

Solution:

Overhead = ISR time / Interval × 100

= 50 / 500 × 100
= 10%

Answer: 10% CPU overhead

Problem 4 — Polling vs Interrupt Comparison

Polling check takes 10 µs each time.
Device becomes ready after 2 ms.

How much CPU time wasted in polling?

Solution:

2 ms = 2000 µs

Checks = 2000 / 10 = 200 polls
CPU time wasted = 200 × 10 µs
= 2000 µs = 2 ms

Answer: 2 ms wasted

Problem 5 — DMA Block Transfer

DMA transfers 1 block = 512 bytes
Transfer speed = 2 MB/s

Find time per block.

Solution:

2 MB/s = 2,000,000 B/s

Time = 512 / 2,000,000
= 0.000256 sec
= 0.256 ms

Answer: 0.256 ms

PART 2 — Numerical on Asynchronous Transfer

Problem 6 — Handshaking Delay

Request signal delay = 3 µs
Acknowledge delay = 2 µs
Data stable time = 5 µs

Find total transfer time per word.

Solution:

Total = 3 + 2 + 5
= 10 µs

Answer: 10 µs

Problem 7 — Strobe Method Error Risk

Sender sends data every 6 µs
Receiver reads every 8 µs

How many transfers lost in 1 ms?

Solution:

Sender sends = 1000 / 6 ≈ 167 words
Receiver reads = 1000 / 8 = 125 words

Lost = 167 − 125
= 42 words

Answer: 42 words lost

Problem 8 — Asynchronous Throughput

Each transfer takes 12 µs.
Find transfers per second.

Solution:

Transfers/sec = 1,000,000 / 12
≈ 83,333 transfers/sec

Answer: ≈ 83,333

PART 3 — Numerical on DMA

Problem 9 — DMA Bus Cycle Stealing

CPU cycle = 200 ns
DMA steals 1 cycle every 5 cycles.

Find CPU slowdown %.

✅ Solution:

DMA steals = 1 / 5 = 20%

Answer: 20% slowdown

Problem 10 — DMA Burst Mode

DMA transfers 1000 words.
Each transfer = 150 ns.

Find burst time.

Solution:

Time = 1000 × 150 ns
= 150,000 ns
= 150 µs

Answer: 150 µs

PART 4 — Numerical on Interrupt System

Problem 11 — Interrupt Priority Encoding

There are 8 interrupt lines.
Find number of encoder output bits required.

Solution:

Bits = log₂(8)
= 3 bits

Answer: 3 bits

Problem 12 — Interrupt Rate

Interrupt occurs every 250 µs.
Find interrupts per second.

Solution:

1 sec = 1,000,000 µs

Interrupts = 1,000,000 / 250
= 4000

Answer: 4000 interrupts/sec

Problem 13 — ISR CPU Usage

ISR time = 30 µs
Interrupt frequency = 5000/sec

Find CPU usage.

Solution:

Total ISR time/sec = 5000 × 30 µs
= 150,000 µs
= 0.15 sec

CPU usage = 15%

Answer: 15%

Problem 14 — Daisy Chain Delay

Each device adds 200 ns delay.
5 devices in chain.

Find total priority resolution delay.

Solution:

Delay = 5 × 200 ns
= 1000 ns = 1 µs

Answer: 1 µs

PART 5 — Mixed Mode Numerical

Problem 15 — Mode Comparison Time

Transfer 10 KB data.

Programmed I/O speed = 100 KB/s
Interrupt I/O speed = 250 KB/s
DMA speed = 2 MB/s

Find times.

Solution:

Programmed I/O:
10 / 100 = 0.1 s

Interrupt I/O:
10 / 250 = 0.04 s

DMA:
10 KB = 0.01 MB
0.01 / 2 = 0.005 s

Answer:
Programmed = 0.1 s
Interrupt = 0.04 s
DMA = 0.005 s

Problem 16 — Handshaking Throughput

Handshake cycle = 15 µs
Find max words/sec.

✅ Solution:

1,000,000 / 15
≈ 66,667 words/sec

Answer: ≈ 66,667

Problem 17 — Interrupt vs Polling CPU Load

Polling takes 12 µs/check
Device ready every 600 µs
ISR time = 20 µs

Compare CPU load.

Solution:

Polling checks = 600/12 = 50 checks
CPU load polling = 600 µs

Interrupt load = 20 µs

Answer: Interrupt saves 580 µs per cycle

Problem 18 — DMA Transfer Cycles

DMA transfers 2048 bytes
Bus width = 16 bits

Find number of transfers.

Solution:

16 bits = 2 bytes

Transfers = 2048 / 2
= 1024

Answer: 1024 transfers

Problem 19 — Interrupt Vector Table Size

System supports 64 interrupts.
Each vector entry = 4 bytes.

Find table size.

Solution:

Size = 64 × 4
= 256 bytes

Answer: 256 bytes

Problem 20 — Bus Utilization

DMA uses bus for 300 µs per ms.

Find bus utilization %.

Solution:

300 / 1000 × 100
= 30%

Answer: 30%

===========================================================

TOPICS:- Direct Memory Access (DMA) — MCQs

Part 1 —MCQs (Direct Memory Access & I/O Processor)

DMA stands for:
A) Direct Memory Allocation
B) Direct Memory Access
C) Data Memory Access
D) Direct Machine Access
Answer: B
DMA allows data transfer between:
A) CPU and Register
B) I/O device and Memory
C) Cache and Register
D) ALU and Memory
Answer: B
DMA transfer occurs without continuous involvement of:
A) RAM
B) CPU
C) Bus
D) Register
Answer: B
The DMA controller takes control of the:
A) Address bus
B) Data bus
C) Control bus
D) System bus
Answer: D
DMA improves system:
A) Cost
B) Speed
C) Size
D) Voltage
Answer: B
In DMA, CPU is interrupted when:
A) Transfer starts
B) Transfer ends
C) Memory full
D) Bus idle
Answer: B
DMA is mainly used for:
A) Slow transfers
B) Bulk data transfer
C) Instruction fetch
D) Cache mapping
Answer: B
Which signal is used to request bus control?
A) HOLD
B) READY
C) RESET
D) INT
Answer: A
CPU acknowledges DMA request using:
A) READY
B) HOLD ACK
C) BUSY
D) INT
Answer: B
DMA controller contains:
A) ALU
B) Program Counter
C) Address Register
D) Stack Pointer
Answer: C

DMA transfer mode where CPU is halted:
A) Burst mode
B) Cycle stealing
C) Transparent
D) Polled
Answer: A
Cycle stealing DMA steals:
A) Instructions
B) Clock cycles
C) Registers
D) Interrupts
Answer: B
Transparent DMA works when:
A) CPU idle
B) CPU busy
C) Memory full
D) Interrupt occurs
Answer: A
DMA reduces CPU:
A) Load
B) Clock speed
C) Registers
D) Power
Answer: A
DMA controller is also called:
A) Bus master
B) Bus slave
C) Decoder
D) Encoder
Answer: A
DMA is commonly used in:
A) Keyboard
B) Disk transfer
C) Mouse
D) Cache
Answer: B
DMA transfer is initiated by:
A) CPU
B) I/O device
C) Memory
D) Cache
Answer: B
DMA controller generates:
A) Memory addresses
B) Opcodes
C) Instructions
D) Flags
Answer: A
DMA needs:
A) Cache
B) Controller hardware
C) Compiler
D) Interpreter
Answer: B
DMA transfer avoids repeated:
A) Interrupts
B) Registers
C) Flags
D) Cache
Answer: A

I/O Processor (IOP) — MCQs

IOP stands for:
A) Input Output Processor
B) Internal Output Processor
C) Instruction Output Processor
D) Input Operation Program
Answer: A
IOP is a:
A) Specialized processor
B) Cache memory
C) Register
D) ALU
Answer: A
IOP executes:
A) User programs
B) I/O programs
C) OS kernel
D) Cache logic
Answer: B
IOP reduces load on:
A) Memory
B) CPU
C) Bus
D) Cache
Answer: B
IOP has its own:
A) Registers
B) Bus
C) Memory
D) All of these
Answer: D
IOP works similar to:
A) Microprocessor
B) Decoder
C) Encoder
D) Multiplexer
Answer: A
IOP handles:
A) Arithmetic
B) I/O tasks
C) Cache mapping
D) Branching
Answer: B
IOP communicates with CPU using:
A) Interrupt
B) Compiler
C) Assembler
D) Loader
Answer: A
IOP improves:
A) Throughput
B) Voltage
C) Heat
D) Power loss
Answer: A
IOP executes instructions stored in:
A) Main memory
B) Cache
C) Register
D) Stack
Answer: A

IOP can control:
A) Multiple I/O devices
B) Only one device
C) Only CPU
D) Only memory
Answer: A
IOP works concurrently with:
A) CPU
B) Cache
C) Register
D) ALU
Answer: A
IOP is used in:
A) High performance systems
B) Only laptops
C) Only mobiles
D) Calculators
Answer: A
IOP has its own:
A) Control unit
B) ALU
C) Registers
D) All
Answer: D
IOP fetches instructions from:
A) I/O memory area
B) Register
C) Cache only
D) ROM only
Answer: A
IOP operation is:
A) Sequential
B) Parallel
C) Random
D) Static
Answer: B
IOP reduces number of:
A) CPU interrupts
B) Registers
C) Memory blocks
D) Flags
Answer: A
IOP is best suited for:
A) Heavy I/O load
B) Math operations
C) Graphics only
D) Cache design
Answer: A
IOP executes:
A) I/O instruction set
B) Machine code only
C) Java code
D) Python code
Answer: A
IOP is also known as:
A) Channel processor
B) Cache unit
C) ALU
D) Decoder
Answer: A

IOP increases:
A) CPU idle time for other work
B) Bus errors
C) Cache misses
D) Power loss
Answer: A
DMA + IOP both aim to:
A) Increase I/O efficiency
B) Reduce RAM
C) Reduce CPU clock
D) Increase heat
Answer: A
IOP can directly access:
A) Main memory
B) Cache only
C) Register only
D) Stack only
Answer: A
IOP sends status via:
A) Interrupt
B) Cache
C) Flag register
D) Bus only
Answer: A
IOP program is called:
A) Channel program
B) User program
C) OS program
D) BIOS program
Answer: A
IOP belongs to:
A) Input Output organization
B) Memory organization
C) CPU design
D) Compiler design
Answer: A
DMA is hardware while IOP is:
A) Programmable processor
B) Cache
C) Register
D) Decoder
Answer: A
IOP provides:
A) Intelligent I/O control
B) Cache mapping
C) Branch prediction
D) Virtual memory
Answer: A
IOP reduces:
A) CPU bottleneck
B) Memory size
C) Bus width
D) Register count
Answer: A
IOP and DMA are used for:
A) Efficient I/O
B) Arithmetic speed
C) Cache mapping
D) Instruction decoding
Answer: A

Part 2 —Fill-in-the-Blanks (with Answers)

DMA stands for Direct Memory Access
DMA transfers data between I/O device and memory
DMA reduces load on CPU
DMA controller takes control of system bus
CPU sends HOLD ACK after receiving HOLD
DMA is used for bulk data transfer
DMA works without continuous CPU control
Burst mode stops the CPU
Cycle stealing steals clock cycles
Transparent DMA works when CPU is idle
DMA controller generates memory addresses
DMA reduces number of interrupts
DMA needs special controller hardware
Disk transfer commonly uses DMA
DMA controller acts as bus master
IOP stands for Input Output Processor
IOP is a specialized processor
IOP executes I/O programs
IOP reduces load on CPU
IOP improves system throughput
IOP has its own registers
IOP communicates using interrupts
IOP can control multiple devices
IOP works parallel with CPU
IOP is used in high performance systems
IOP fetches instructions from main memory
IOP has its own control unit
IOP executes channel programs
IOP is also called channel processor
IOP provides intelligent I/O control
DMA and IOP increase I/O efficiency
IOP directly accesses memory
IOP reduces CPU interrupts
IOP handles heavy I/O load
DMA avoids repeated interrupts
DMA controller contains address register
DMA request comes from I/O device
DMA acknowledgment comes from CPU
IOP executes separate instruction set
IOP increases CPU availability
DMA is a hardware technique
IOP is a programmable unit
DMA improves transfer speed
IOP reduces CPU bottleneck
IOP manages I/O operations
Transparent DMA uses idle bus cycles
Burst DMA gives full control to DMA controller
Cycle stealing mode shares bus
IOP and DMA belong to I/O organization
Both DMA and IOP improve performance

============================================================

TOPICS:- DMA Numerical Questions

MCQs

A DMA controller transfers 4096 bytes at a rate of 2 MB/s. How much time is required?

Answer:
Rate = 2 MB/s = 2 × 10⁶ B/s
Time = Data / Rate = 4096 / (2×10⁶)
= 0.002048 s = 2.048 ms

DMA transfers 8 KB block using burst mode at 4 MB/s. Find transfer time.

Answer:
8 KB = 8192 bytes
Time = 8192 / (4×10⁶) = 0.002048 s = 2.048 ms

A DMA steals one bus cycle every 5 CPU cycles. CPU cycle = 100 ns. Find % CPU slowdown.

Answer:
1 out of 5 cycles stolen
Slowdown = 1/5 = 20%

DMA transfers 2048 words, word size = 4 bytes, rate = 1 MB/s. Time?

Answer:
Data = 2048 × 4 = 8192 bytes
Time = 8192 / 10⁶ = 8.192 ms

DMA address register is 16-bit. Max memory it can address?

Answer:
2¹⁶ = 65,536 bytes = 64 KB

DMA counter register is 12-bit. Max block size?

Answer:
2¹² = 4096 transfers

DMA transfer rate = 10 MB/s. Data block = 50 KB. Time?

Answer:
50 KB = 51200 B
Time = 51200 / (10×10⁶)
= 5.12 ms

DMA takes 200 ns per word. Transfer 5000 words. Time?

Answer:
Time = 5000 × 200 ns
= 1,000,000 ns = 1 ms

CPU bus cycle = 80 ns. DMA steals every 4th cycle. Effective CPU cycle available?

Answer:
Available = 3/4
Effective = 0.75 × 80 = 60 ns useful

Q10

DMA transfers 1 MB in 0.25 sec. Find rate.

Answer:
Rate = 1 MB / 0.25 s
= 4 MB/s

Q11

DMA block transfer = 32 KB at 8 MB/s + setup overhead 0.5 ms. Total time?

Answer:
32 KB = 32768 B
Transfer time = 32768 / (8×10⁶) = 4.096 ms
Total = 4.096 + 0.5 = 4.596 ms

Q12

DMA steals 10% cycles. CPU execution time without DMA = 100 ms. New time?

Answer:
New time = 100 / 0.9
= 111.1 ms

Q13

DMA moves 10,000 words, 2 bytes each, at 5 MB/s. Time?

Answer:
Data = 20,000 B
Time = 20000 / (5×10⁶)
= 4 ms

Q14

Bus width = 32 bits. DMA clock = 25 MHz. Max transfer rate?

Answer:
32 bits = 4 bytes
Rate = 4 × 25M = 100 MB/s

Q15

DMA register = 14-bit address. Addressable memory?

Answer:
2¹⁴ = 16 KB

Q16

DMA burst = 1000 bytes, bus rate = 50 MB/s. Time?

Answer:
1000 / (50×10⁶) = 0.02 ms

Q17

DMA overhead per block = 200 µs. 20 blocks transferred. Total overhead?

Answer:
= 200 × 20 = 4000 µs = 4 ms

Q18

DMA transfer = 256 KB at 16 MB/s. Time?

Answer:
256 KB = 262144 B
Time = 262144 / (16×10⁶)
= 16.38 ms

Q19

DMA cycle stealing every 10 cycles. CPU cycle = 50 ns. Loss per 1000 cycles?

Answer:
Stolen = 100 cycles
Time lost = 100 × 50 ns = 5000 ns = 5 µs

Q20

DMA word = 8 bytes. Transfer 4096 words. Total bytes?

Answer:
4096 × 8 = 32768 bytes

Q21

DMA speed = 20 MB/s. Needed to transfer 2 MB. Time?

Answer:
2 / 20 = 0.1 sec

Q22

DMA counter = 10-bit. Max count?

Answer:
2¹⁰ = 1024

Q23

DMA takes 120 ns/transfer. 10,000 transfers. Time?

Answer:
= 1.2 ms

Q24

DMA burst block = 64 KB at 32 MB/s. Time?

Answer:
= 2 ms

Q25

DMA steals 5% CPU cycles. CPU job = 200 ms. New time?

Answer:
200 / 0.95 = 210.5 ms

Part B — I/O Processor Numerical Questions

Q26

IOP processes 5000 I/O ops/sec. Each op = 2 ms CPU time saved. Total CPU time saved/sec?

Answer:
5000 × 2 ms = 10,000 ms = 10 sec

Q27

Without IOP CPU handles 3000 I/O ops taking 0.5 ms each. With IOP only 10% CPU needed. New CPU time?

Answer:
Old = 3000 × 0.5 = 1500 ms
New = 10% = 150 ms

Q28

IOP transfer rate = 40 MB/s. Disk block = 80 KB. Time?

Answer:
= 2 ms

Q29

IOP executes 200K instructions/sec. Program = 5000 instructions. Time?

Answer:
5000 / 200000 = 0.025 sec

Q30

IOP reduces CPU I/O wait from 30% to 5%. CPU job = 2 sec. Time saved?

Answer:
Old wait = 0.6 s
New wait = 0.1 s
Saved = 0.5 sec

Q31

IOP channel bandwidth = 100 MB/s. Transfer 25 MB. Time?

Answer:
= 0.25 sec

Q32

IOP handles 8 devices each sending 2 MB/s. Total bandwidth needed?

Answer:
= 16 MB/s

Q33

CPU interrupt handling time = 50 µs. IOP reduces interrupts from 10,000 to 500. Time saved?

Answer:
Old = 0.5 s
New = 0.025 s
Saved = 0.475 s

Q34

IOP program length = 2000 instructions. Speed = 1 MIPS. Time?

Answer:
= 2 ms

Q35

IOP + DMA combined rate = 60 MB/s. Data = 120 MB. Time?

Answer:
= 2 sec

Q36

Without IOP throughput = 200 ops/sec. With IOP = 800 ops/sec. Improvement factor?

Answer:
800/200 = 4×

Q37

IOP reduces CPU I/O cycles by 70%. CPU used 10M cycles. New cycles?

Answer:
= 3M cycles

Q38

IOP memory buffer = 64 KB. Each record = 512 B. Records stored?

Answer:
= 128

Q39

IOP executes command in 25 µs. 400 commands. Time?

Answer:
= 10 ms

Q40

IOP transfer = 10 GB at 200 MB/s. Time?

Answer:
= 50 sec

===============================================================

TOPICS :- Computer Organization – Memory Organization: Types & Capacity of Memory.

MCQs (With Answers)

1. Which memory is fastest?
A) RAM B) ROM C) Cache D) Hard Disk
Answer: C

2. Which memory is volatile?
A) ROM B) RAM C) HDD D) DVD
Answer: B

3. Cache memory is placed between:
A) CPU & RAM
B) RAM & HDD
C) CPU & HDD
D) ROM & RAM
Answer: A

4. Which is non-volatile memory?
A) SRAM B) DRAM C) ROM D) Cache
Answer: C

5. Primary memory is also called:
A) Secondary memory
B) Main memory
C) Backup memory
D) Virtual memory
Answer: B

6. Secondary memory is:
A) Faster than RAM
B) Non-volatile
C) Inside CPU
D) Volatile
Answer: B

7. SRAM stands for:
A) Static RAM
B) Serial RAM
C) Secondary RAM
D) Simple RAM
Answer: A

8. DRAM requires:
A) No refresh
B) Constant refresh
C) Formatting
D) Cooling
Answer: B

9. Which is cheaper?
A) SRAM B) Cache C) DRAM D) Register
Answer: C

10. Registers are located in:
A) RAM
B) CPU
C) ROM
D) Disk
Answer: B

11. Which memory has highest capacity?
A) Register B) Cache C) RAM D) Hard Disk
Answer: D

12. Memory hierarchy is arranged by:
A) Speed & Cost
B) Color
C) Shape
D) Brand
Answer: A

13. Virtual memory uses:
A) Cache
B) Hard disk
C) Register
D) ROM
Answer: B

14. EEPROM stands for:
A) Electrically Erasable PROM
B) Easily Erased PROM
C) External PROM
D) Extra PROM
Answer: A

15. PROM can be programmed:
A) Many times
B) Once
C) Never
D) Twice
Answer: B

16. Which is read-only memory?
A) RAM B) ROM C) Cache D) Register
Answer: B

17. Cache improves:
A) Cost
B) Speed
C) Size
D) Power use
Answer: B

18. Which is smallest in size?
A) Cache B) Register C) RAM D) Disk
Answer: B

19. Memory access time is lowest for:
A) Disk B) RAM C) Cache D) Register
Answer: D

20. Secondary storage example:
A) RAM B) ROM C) SSD D) Cache
Answer: C

21. Flash memory is a type of:
A) ROM
B) RAM
C) Cache
D) Register
Answer: A

22. Which is volatile?
A) Flash B) HDD C) DRAM D) DVD
Answer: C

23. Memory hierarchy top level:
A) Disk B) Cache C) Register D) RAM
Answer: C

24. Memory hierarchy bottom level:
A) Register B) Cache C) Disk D) RAM
Answer: C

25. Which is fastest RAM type?
A) DRAM B) SRAM C) SDRAM D) DDR
Answer: B

26. Cache is built using:
A) DRAM B) SRAM C) ROM D) Flash
Answer: B

27. Main memory is directly accessed by:
A) Printer B) CPU C) User D) Mouse
Answer: B

28. Which memory stores BIOS?
A) RAM B) ROM C) Cache D) Register
Answer: B

29. DDR stands for:
A) Double Data Rate
B) Dual Data RAM
C) Double Dynamic RAM
D) Disk Data Rate
Answer: A

30. Memory unit KB equals:
A) 1000 bytes
B) 1024 bytes
C) 512 bytes
D) 2048 bytes
Answer: B

31. 1 MB equals:
A) 1024 KB
B) 1000 KB
C) 512 KB
D) 2048 KB
Answer: A

32. Hard disk is:
A) Primary
B) Secondary
C) Cache
D) Register
Answer: B

33. Access time is highest in:
A) Register
B) Cache
C) RAM
D) Disk
Answer: D

34. Which memory is closest to CPU?
A) Disk B) RAM C) Cache D) DVD
Answer: C

35. Which stores temporary data?
A) ROM B) RAM C) DVD D) Flash
Answer: B

36. Memory hierarchy reduces:
A) Cost & Access time
B) Power only
C) Size only
D) Heat
Answer: A

37. Magnetic storage example:
A) HDD
B) SSD
C) RAM
D) Cache
Answer: A

38. Optical storage example:
A) CD
B) RAM
C) Cache
D) Register
Answer: A

39. Which memory is programmable once?
A) PROM
B) EEPROM
C) RAM
D) Cache
Answer: A

40. Secondary memory is also called:
A) Auxiliary memory
B) Main memory
C) Cache
D) Register
Answer: A

41. Memory capacity is measured in:
A) Bits & Bytes
B) Volts
C) Hertz
D) Watts
Answer: A

42. Which is not primary memory?
A) RAM
B) ROM
C) Cache
D) HDD
Answer: D

43. Cache hit means:
A) Data found in cache
B) Cache error
C) Cache full
D) Cache empty
Answer: A

44. Cache miss means:
A) Data not in cache
B) Cache broken
C) Cache full
D) Cache locked
Answer: A

45. L1 cache is:
A) Slowest
B) Closest to CPU
C) Biggest
D) External
Answer: B

46. L3 cache is:
A) Larger but slower
B) Fastest
C) Smallest
D) ROM
Answer: A

47. Virtual memory gives illusion of:
A) Larger RAM
B) Smaller RAM
C) Faster CPU
D) Larger disk
Answer: A

48. Which is fastest storage device?
A) SSD
B) HDD
C) Register
D) DVD
Answer: C

49. DRAM is used as:
A) Cache
B) Main memory
C) Register
D) ROM
Answer: B

50. Memory hierarchy is based on:
A) Speed, Cost, Capacity
B) Color
C) Weight
D) Shape
Answer: A

Part 2 —Fill in the Blanks (Question–Answer Format)

1. Fastest memory is ______ → Register
2. Cache is between CPU and ______ → RAM
3. RAM is ______ memory → Volatile
4. ROM is ______ memory → Non-volatile
5. DRAM needs periodic ______ → Refresh
6. SRAM means ______ → Static Random Access Memory
7. Main memory is also called ______ → Primary memory
8. Hard disk is ______ memory → Secondary
9. Memory unit KB = ______ bytes → 1024
10. PROM can be programmed only ______ → Once
11. EEPROM is electrically ______ → Erasable
12. Cache uses ______ technology → SRAM
13. Virtual memory uses ______ storage → Disk
14. Smallest memory unit is ______ → Bit
15. 8 bits = 1 ______ → Byte
16. L1 cache is ______ to CPU → Closest
17. Memory hierarchy reduces access ______ → Time
18. Optical storage example ______ → CD/DVD
19. Magnetic storage example ______ → Hard disk
20. BIOS is stored in ______ → ROM
21. DDR stands for ______ → Double Data Rate
22. DRAM is ______ than SRAM → Slower
23. SRAM is ______ than DRAM → Faster
24. Secondary memory is also called ______ → Auxiliary memory
25. Cache miss means data not found in ______ → Cache
26. Cache hit means data found in ______ → Cache
27. Flash memory is type of ______ → ROM
28. Register is inside ______ → CPU
29. Memory capacity measured in ______ → Bytes
30. Top of hierarchy is ______ → Register
31. Bottom of hierarchy is ______ → Secondary storage
32. RAM stores ______ data → Temporary
33. ROM stores ______ instructions → Permanent
34. L3 cache is ______ than L1 → Slower
35. SSD is ______ storage → Secondary
36. Memory directly accessed by CPU is ______ → Main memory
37. PROM stands for ______ → Programmable Read Only Memory
38. EPROM is erased by ______ → UV light
39. Memory near CPU improves ______ → Performance
40. Larger memory usually has ______ speed → Lower
41. Registers have ______ capacity → Very small
42. Disk has ______ capacity → Very large
43. Cache is ______ than RAM → Faster
44. RAM is ______ than disk → Faster
45. Memory hierarchy balances cost and ______ → Speed
46. Virtual memory increases logical ______ → Memory
47. Secondary storage is ______ volatile → Non
48. Primary memory is mostly ______ volatile → Volatile
49. DRAM stands for ______ → Dynamic Random Access Memory
50. Memory organization deals with storage ______ → Structure

==============================================================

Topics: Associative Memory, Buffer, Cache Memory, Virtual Memory

Format: MCQs

Part A —MCQs (Multiple Choice Questions)

Associative Memory

1. Associative memory is also known as:
A. Virtual memory
B. Content Addressable Memory
C. Auxiliary memory
D. Flash memory
Answer: B

2. Associative memory searches data by using:
A. Address
B. Index
C. Content
D. Pointer
Answer: C

3. CAM stands for:
A. Computer Access Memory
B. Content Addressable Memory
C. Cache Access Module
D. Central Address Memory
Answer: B

4. Associative memory is mainly used in:
A. Registers
B. Cache memory
C. Hard disk
D. ROM
Answer: B

5. Associative memory provides:
A. Sequential search
B. Parallel search
C. Manual search
D. Binary search
Answer: B

6. Access time of associative memory is:
A. Very high
B. Very low (fast)
C. Equal to RAM
D. Equal to disk
Answer: B

7. Associative memory compares input with:
A. All stored words
B. One word only
C. First word only
D. Last word only
Answer: A

8. Major disadvantage of associative memory is:
A. Slow speed
B. High cost
C. Small size only
D. Low reliability
Answer: B

9. Associative memory hardware is:
A. Simple
B. Complex
C. Mechanical
D. Magnetic
Answer: B

10. Associative memory is useful in:
A. Address translation
B. Keyboard input
C. Printer output
D. Sound processing
Answer: A

Buffer Memory

11. A buffer is used to:
A. Increase CPU speed
B. Temporarily store data
C. Permanently store data
D. Encrypt data
Answer: B

12. Buffer memory helps in:
A. Speed matching
B. Virus removal
C. Formatting
D. Compression
Answer: A

13. Buffer is mainly placed between:
A. Two devices with different speeds
B. Two CPUs
C. Two monitors
D. Two printers
Answer: A

14. Keyboard buffer stores:
A. Screen output
B. Keystrokes temporarily
C. BIOS data
D. Cache tags
Answer: B

15. Buffer reduces:
A. Power
B. Speed difference impact
C. Storage size
D. Instruction count
Answer: B

16. Buffer memory is:
A. Permanent
B. Temporary
C. Secondary
D. Optical
Answer: B

17. Printer spooler is an example of:
A. Buffering
B. Caching
C. Paging
D. Mapping
Answer: A

18. Buffer overflow occurs when:
A. Buffer is empty
B. Data exceeds buffer size
C. CPU is idle
D. Cache is full
Answer: B

19. Double buffering uses:
A. Two buffers
B. One buffer
C. Three buffers
D. No buffer
Answer: A

20. Buffer improves:
A. Data transfer efficiency
B. Disk capacity
C. CPU architecture
D. Instruction set
Answer: A

Cache Memory

21. Cache memory is located between:
A. CPU and main memory
B. RAM and disk
C. Disk and printer
D. Monitor and CPU
Answer: A

22. Cache memory is:
A. Slower than RAM
B. Faster than RAM
C. Equal to disk
D. Optical
Answer: B

23. Cache is built using:
A. DRAM
B. SRAM
C. Flash
D. ROM
Answer: B

24. Cache stores:
A. All data
B. Frequently used data
C. Old data only
D. Backup data
Answer: B

25. Cache improves:
A. Access time
B. File size
C. Screen resolution
D. Power usage
Answer: A

26. L1 cache is:
A. Slowest
B. Closest to CPU
C. Largest
D. On disk
Answer: B

27. Cache miss means:
A. Data found in cache
B. Data not found in cache
C. Cache error
D. Cache disabled
Answer: B

28. Cache hit ratio should be:
A. Low
B. High
C. Zero
D. Negative
Answer: B

29. Mapping technique NOT used in cache:
A. Direct mapping
B. Associative mapping
C. Set associative
D. Virtual mapping
Answer: D

30. Cache replacement policy example:
A. FIFO
B. LRU
C. Random
D. All of these
Answer: D

Virtual Memory

31. Virtual memory gives illusion of:
A. Larger memory
B. Smaller CPU
C. Faster disk
D. More cache
Answer: A

32. Virtual memory uses:
A. Hard disk space
B. Register space
C. GPU memory
D. ROM
Answer: A

33. Virtual memory is implemented using:
A. Paging
B. Segmentation
C. Both A and B
D. None
Answer: C

34. Page fault occurs when:
A. Page is found
B. Page not in RAM
C. Cache full
D. Buffer empty
Answer: B

35. Virtual memory is managed by:
A. Compiler
B. Operating System
C. User
D. BIOS
Answer: B

36. Thrashing happens when:
A. Too many page faults
B. CPU idle
C. Disk full
D. Cache hit
Answer: A

37. Page replacement algorithm example:
A. LRU
B. FIFO
C. Optimal
D. All of these
Answer: D

38. Virtual address is converted to physical address using:
A. ALU
B. MMU
C. CU
D. Register
Answer: B

39. Demand paging loads page when:
A. Program starts
B. Needed
C. System boots
D. Cache miss
Answer: B

40. Page table stores:
A. File names
B. Address mapping
C. Cache tags
D. Buffer size
Answer: B

Mixed Concept MCQs

41. Fastest memory among these: Cache
Answer: Cache

42. CAM is used in: Cache lookup
Answer: Cache lookup

43. Buffer mainly handles: I/O speed difference
Answer: I/O speed difference

44. Virtual memory increases: Logical address space
Answer: Logical address space

45. LRU stands for: Least Recently Used
Answer: Least Recently Used

46. Cache uses locality principle: Yes
Answer: Yes

47. Page size is usually: Fixed
Answer: Fixed

48. TLB is related to: Virtual memory
Answer: Virtual memory

49. Cache tag stores: Address info
Answer: Address info

50. Buffering reduces: Waiting time
Answer: Waiting time

Part B —Fill in the Blanks (with Answers)

Associative memory is also called Content Addressable Memory.
Associative memory searches using content.
CAM performs parallel comparison.
Associative memory hardware is complex.
Cache lookup uses associative search.
Buffer memory is temporary storage.
Buffer is used between devices of different speeds.
Keyboard uses a buffer.
Printer queue is called spooling.
Buffer overflow happens when buffer is full.
Cache memory is placed between CPU and main memory.
Cache is faster than RAM.
Cache uses SRAM technology.
Cache stores frequently used data.
L1 cache is closest to CPU.
L2 cache is larger than L1.
Cache hit means data is found.
Cache miss means data is not found.
LRU means Least Recently Used.
FIFO means First In First Out.
Direct mapping maps one block to one line.
Fully associative mapping allows block in any line.
Set associative is combination of direct and associative.
Cache improves access time.
Cache works on locality of reference.
Virtual memory uses disk space.
Virtual memory gives illusion of large memory.
Paging divides memory into pages.
Segmentation divides memory into segments.
Page fault occurs when page is not in RAM.
MMU stands for Memory Management Unit.
Page table stores mapping.
Thrashing means too many page faults.
Demand paging loads pages on demand.
TLB stands for Translation Lookaside Buffer.
Virtual address is also called logical address.
Physical address is generated by MMU.
Replacement policy decides which page to remove.
Optimal replacement gives minimum faults.
Working set reduces thrashing.
Cache tag stores address bits.
Write-through updates memory immediately.
Write-back updates later on replacement.
Double buffering uses two buffers.
Circular buffer is also called ring buffer.
Cache controller manages cache operations.
Hit ratio should be high.
Miss penalty is extra time.
Virtual memory is handled by OS.
Buffer improves data transfer efficiency.

======================================================

*************************************************************************

DR. PANKAJ DADHICH

Computer Organizations- Question Paper- 4