Computer Organizations- Question Paper- 3

Topics:- Combinational Circuits: Half Adder, Full Adder, Decoders, Multiplexers.

Part A —MCQs (with Answers)

Half Adder & Full Adder (MCQs)

A half adder adds how many bits?
A) 1 B) 2 C) 3 D) 4
Answer: B
Half adder produces outputs:
A) Sum only
B) Carry only
C) Sum and Carry
D) Difference and Borrow
Answer: C
Sum output of half adder is:
A) AND
B) OR
C) XOR
D) NOR
Answer: C
Carry output of half adder is:
A) AND
B) XOR
C) OR
D) NAND
Answer: A
Full adder adds how many input bits?
A) 2
B) 3
C) 4
D) 1
Answer: B
Full adder outputs are:
A) Sum, Carry
B) Sum only
C) Carry only
D) Difference
Answer: A
A full adder can be built using:
A) 1 half adder
B) 2 half adders + OR gate
C) 3 half adders
D) XOR only
Answer: B
Sum of full adder equals:
A) A+B+C
B) A AND B
C) A ⊕ B ⊕ Cin
D) A OR B
Answer: C
Carry of full adder equals:
A) AB + BC + AC
B) A+B+C
C) A⊕B
D) AB
Answer: A
Half adder cannot handle:
A) Input bits
B) Carry input
C) Sum output
D) Carry output
Answer: B

🔹 Decoder MCQs

A decoder converts:
A) Binary to decimal
B) Decimal to binary
C) Analog to digital
D) Serial to parallel
Answer: A
A 2-to-4 decoder has outputs:
A) 2
B) 3
C) 4
D) 8
Answer: C
A 3-to-8 decoder has input lines:
A) 2
B) 3
C) 4
D) 8
Answer: B
Number of outputs of n-input decoder =
A) n
B) 2n
C) n²
D) 2ⁿ
Answer: D
Decoder is also called:
A) Data selector
B) Line selector
C) Code converter
D) Encoder
Answer: B
Enable pin in decoder is used to:
A) Disable circuit
B) Activate circuit
C) Add inputs
D) Reduce outputs
Answer: B
4-to-16 decoder has outputs:
A) 8
B) 12
C) 16
D) 32
Answer: C
Decoder outputs are usually:
A) Active low/high
B) Floating
C) Analog
D) Random
Answer: A
Decoder is a:
A) Sequential circuit
B) Combinational circuit
C) Memory
D) Counter
Answer: B
Which device is opposite of decoder?
A) Encoder
B) Adder
C) MUX
D) Counter
Answer: A

🔹 Multiplexer MCQs

Multiplexer is also called:
A) Data selector
B) Data adder
C) Data decoder
D) Counter
Answer: A
A 4-to-1 MUX has select lines:
A) 1
B) 2
C) 3
D) 4
Answer: B
Number of select lines =
A) log₂(inputs)
B) inputs²
C) inputs/2
D) outputs
Answer: A
8-to-1 MUX select lines:
A) 2
B) 3
C) 4
D) 8
Answer: B
MUX selects:
A) One input
B) All inputs
C) No input
D) Two inputs
Answer: A
MUX output lines:
A) 1
B) 2
C) n
D) 0
Answer: A
MUX works like:
A) Switch
B) Counter
C) Register
D) Decoder
Answer: A
A 16-to-1 MUX needs select lines:
A) 2
B) 3
C) 4
D) 5
Answer: C
MUX is a:
A) Storage device
B) Combinational device
C) Sequential device
D) Memory
Answer: B
Which is used in data routing?
A) MUX
B) Adder
C) Counter
D) Register
Answer: A

🔹 Mixed Concept MCQs

Half adder uses gates:
A) XOR, AND
B) OR, NOT
C) NAND only
D) NOR only
Answer: A
Full adder carry uses:
A) OR of AND terms
B) XOR only
C) NOT only
D) NAND
Answer: A
Decoder output lines are:
A) Mutually exclusive
B) All high
C) All low
D) Floating
Answer: A
MUX reduces:
A) Data lines
B) Output lines
C) Memory
D) Clock
Answer: A
Decoder increases:
A) Inputs
B) Outputs
C) Clock
D) Memory
Answer: B
Half adder is used in:
A) Basic addition
B) Division
C) Storage
D) Counting
Answer: A
Full adder includes:
A) Carry input
B) Clock
C) Reset
D) Enable only
Answer: A
3-to-8 decoder outputs active lines:
A) One
B) Two
C) Three
D) All
Answer: A
MUX is controlled by:
A) Select lines
B) Data lines
C) Carry
D) Clock
Answer: A
Decoder select lines equal:
A) Input lines
B) Output lines
C) Carry lines
D) Sum lines
Answer: A
Full adder sum uses:
A) Triple XOR
B) AND
C) OR
D) NAND
Answer: A
Half adder carry formula:
A) A+B
B) AB
C) A⊕B
D) A’B
Answer: B
MUX output depends on:
A) Selected input
B) All inputs
C) None
D) Clock
Answer: A
Decoder is used in:
A) Memory address selection
B) Counting
C) Timing
D) Oscillation
Answer: A
Full adder requires half adders:
A) Two
B) Three
C) Four
D) One
Answer: A
2-to-4 decoder has select lines:
A) 1
B) 2
C) 3
D) 4
Answer: B
MUX selects using:
A) Control bits
B) Power bits
C) Clock bits
D) Reset bits
Answer: A
Decoder output count formula:
A) n²
B) 2ⁿ
C) n+2
D) n−1
Answer: B
Half adder cannot cascade because no:
A) Sum
B) Carry input
C) XOR
D) AND
Answer: B
Full adder is used in:
A) Multi-bit addition
B) Display
C) Storage
D) Encoding
Answer: A

Part B — Fill in the Blanks (with Answers)

Half adder adds ______ bits. → 2
Half adder outputs are ______ and ______. → Sum, Carry
Half adder sum uses ______ gate. → XOR
Half adder carry uses ______ gate. → AND
Full adder has ______ inputs. → 3
Full adder outputs ______ and ______. → Sum, Carry
Full adder includes carry ______. → input
Full adder sum = A ⊕ B ⊕ ______. → Cin
Decoder is a ______ circuit. → combinational
Decoder converts binary to ______. → one-hot output/decimal
n-input decoder has ______ outputs. → 2ⁿ
3-to-8 decoder has ______ outputs. → 8
Decoder has an ______ pin. → enable
Only one decoder output is ______ at a time. → active
Decoder selects ______ line. → one
Multiplexer is also called data ______. → selector
MUX selects one of many ______. → inputs
4-to-1 MUX has ______ select lines. → 2
8-to-1 MUX has ______ select lines. → 3
MUX gives ______ output. → single
Select lines formula = log₂ ______. → inputs
Half adder carry = A ______ B. → AND
Half adder sum = A ______ B. → XOR
Full adder carry = AB + BC + ______. → AC
Full adder can be built using ______ half adders. → two
Decoder is opposite of ______. → encoder
MUX reduces number of ______ lines. → data
Decoder increases number of ______ lines. → output
Full adder is used for ______ bit addition. → multi
Half adder cannot accept ______ input. → carry
A 2-to-4 decoder has ______ inputs. → 2
A 4-to-16 decoder has ______ outputs. → 16
MUX works like a digital ______. → switch
Decoder outputs are mutually ______. → exclusive
MUX is a ______ circuit. → combinational
Full adder sum uses ______ XOR gates. → two
Full adder carry uses ______ gates. → AND-OR
Enable = 0 usually ______ decoder. → disables
MUX control signals are called ______ lines. → select
Decoder is used in memory ______. → addressing
Half adder is simplest ______ circuit. → adder
Full adder has carry ______ and carry ______. → in, out
16-to-1 MUX needs ______ select lines. → 4
2ⁿ outputs need ______ inputs in decoder. → n
MUX output depends on ______ input. → selected
Decoder activates ______ output line. → one
XOR gate gives sum without ______. → carry
AND gate generates ______ in adder. → carry
Combinational circuits have no ______. → memory
Adders are ______ circuits. → combinational

==================================================================

Topics :- Sequential Circuits – Flip-Flops (SR, JK, D, T), Excitation Tables, State Diagram, State Table

PART 1 —MCQs (Sequential Circuits & Flip-Flops)

1. Sequential circuits differ from combinational circuits because they have:
A) Only inputs
B) Only outputs
C) Memory
D) No logic gates
Answer: C

2. The basic memory element in sequential circuits is:
A) Counter
B) Register
C) Flip-flop
D) Decoder
Answer: C

3. An SR flip-flop has how many inputs?
A) 1
B) 2
C) 3
D) 4
Answer: B

4. SR stands for:
A) Set–Reset
B) Start–Run
C) Set–Read
D) Save–Reset
Answer: A

5. Invalid condition of SR flip-flop occurs when:
A) S=0, R=0
B) S=1, R=0
C) S=0, R=1
D) S=1, R=1
Answer: D

6. JK flip-flop removes the invalid condition of:
A) D FF
B) SR FF
C) T FF
D) Latch
Answer: B

7. When J=K=1, JK flip-flop will:
A) Reset
B) Set
C) Toggle
D) Hold
Answer: C

8. D flip-flop is also known as:
A) Delay FF
B) Data FF
C) Both A and B
D) Dual FF
Answer: C

9. In D flip-flop, output equals input at:
A) Any time
B) Clock edge
C) Reset
D) Power off
Answer: B

10. T flip-flop toggles when:
A) T=0
B) T=1
C) T=2
D) T=X
Answer: B

11. T flip-flop can be derived from:
A) SR FF
B) JK FF
C) D FF
D) Counter
Answer: B

12. Number of stable states in a flip-flop:
A) 1
B) 2
C) 3
D) Infinite
Answer: B

13. Flip-flops are triggered by:
A) Voltage only
B) Current only
C) Clock
D) Resistance
Answer: C

14. Edge-triggered flip-flop changes state at:
A) Input change
B) Clock edge
C) Power on
D) Reset
Answer: B

15. State table represents:
A) Logic gates
B) Present & next states
C) Only outputs
D) Only inputs
Answer: B

16. State diagram is a:
A) Graphical representation
B) Equation
C) Table
D) Formula
Answer: A

17. Excitation table shows:
A) Required inputs for transition
B) Outputs only
C) Power values
D) Gate delays
Answer: A

18. In SR FF, S=1, R=0 gives:
A) Reset
B) Set
C) Toggle
D) No change
Answer: B

19. In SR FF, S=0, R=1 gives:
A) Reset
B) Set
C) Toggle
D) Hold
Answer: A

20. In JK FF, J=0, K=0 gives:
A) Toggle
B) Reset
C) No change
D) Set
Answer: C

21. D flip-flop eliminates:
A) Toggle
B) Race
C) Invalid input
D) Clock
Answer: C

22. Flip-flops are built using:
A) NAND/NOR gates
B) Adders
C) Encoders
D) Multipliers
Answer: A

23. Memory element stores:
A) Analog value
B) One bit
C) One byte
D) Word
Answer: B

24. Sequential circuit output depends on:
A) Input only
B) Past state only
C) Input and previous state
D) Clock only
Answer: C

25. Clocked SR FF is also called:
A) Gated SR FF
B) D FF
C) T FF
D) JK FF
Answer: A

26. Race around condition occurs in:
A) D FF
B) T FF
C) JK FF
D) SR latch
Answer: C

27. Race condition occurs when clock pulse is:
A) Too short
B) Too long
C) Missing
D) Zero
Answer: B

28. Master-slave FF solves:
A) Noise
B) Race around
C) Power loss
D) Delay
Answer: B

29. Output of T FF when T=0:
A) Toggle
B) Reset
C) No change
D) Set
Answer: C

30. Number of states in one flip-flop:
A) 1
B) 2
C) 4
D) 8
Answer: B

31. State diagram uses:
A) Circles
B) Squares
C) Triangles
D) Lines
Answer: A

32. State transitions are shown by:
A) Arrows
B) Boxes
C) Tables
D) Circles
Answer: A

33. D flip-flop next state equals:
A) Clock
B) D input
C) Reset
D) Toggle
Answer: B

34. JK with J=1 K=0 behaves like:
A) Reset
B) Set
C) Toggle
D) Hold
Answer: B

35. JK with J=0 K=1 behaves like:
A) Set
B) Toggle
C) Reset
D) Hold
Answer: C

36. T flip-flop is used in:
A) Counters
B) Adders
C) Encoders
D) MUX
Answer: A

37. Flip-flop output is represented by:
A) Q
B) P
C) Z
D) X
Answer: A

38. Complement output is:
A) Q
B) Q'
C) D
D) T
Answer: B

39. Sequential circuits need:
A) Feedback
B) Only input
C) No clock
D) Only output
Answer: A

40. SR latch built using NOR gates is:
A) Active low
B) Active high
C) Edge triggered
D) Level free
Answer: B

41. Edge triggering avoids:
A) Memory
B) Errors
C) Multiple transitions
D) Power
Answer: C

42. State table columns include:
A) Present & next state
B) Only outputs
C) Only inputs
D) Only states
Answer: A

43. Excitation table is reverse of:
A) Truth table
B) State table
C) Output table
D) Logic table
Answer: B

44. Flip-flop is also called:
A) Bistable
B) Monostable
C) Astable
D) Multivibrator only
Answer: A

45. SR FF invalid input produces:
A) Known state
B) Unknown state
C) Reset
D) Toggle
Answer: B

46. D FF prevents:
A) Toggle
B) Invalid state
C) Reset
D) Clock
Answer: B

47. Sequential logic always has:
A) Memory
B) No gates
C) Only AND
D) Only OR
Answer: A

48. Flip-flop changes output when:
A) Clock triggers
B) Input changes only
C) Power off
D) Reset only
Answer: A

49. State diagram is useful for:
A) Visualization
B) Power saving
C) Speed
D) Wiring
Answer: A

50. Minimum flip-flop stores:
A) 2 bits
B) 4 bits
C) 1 bit
D) 8 bits
Answer: C

PART 2 —Fill in the Blanks (with Answers)

Sequential circuits have ______.
Answer: memory
Flip-flop stores ______ bit.
Answer: one
SR stands for ______ and ______.
Answer: Set, Reset
Invalid state in SR FF occurs when S=__ and R=__.
Answer: 1, 1
JK FF removes ______ condition.
Answer: invalid
When J=K=1, JK FF ______.
Answer: toggles
D flip-flop is also called ______ flip-flop.
Answer: data
T flip-flop toggles when T = ______.
Answer: 1
Flip-flops are ______ devices.
Answer: bistable
Sequential circuit output depends on ______ and ______.
Answer: input, previous state
Clock signal is used for ______.
Answer: triggering
State diagram is ______ representation.
Answer: graphical
State table shows ______ and ______ states.
Answer: present, next
Excitation table shows required ______.
Answer: inputs
Output of flip-flop is denoted by ______.
Answer: Q
Complement output is ______.
Answer: Q'
D FF next state equals ______.
Answer: D
JK race around occurs when clock is too ______.
Answer: long
Master-slave FF prevents ______ condition.
Answer: race around
T FF is used in ______.
Answer: counters
Flip-flops are built using ______ gates.
Answer: NAND/NOR
SR FF has ______ inputs.
Answer: two
Memory element is called ______.
Answer: flip-flop
Edge-triggered FF changes on clock ______.
Answer: edge
Sequential circuits use ______.
Answer: feedback
JK FF with J=0 K=0 gives ______.
Answer: no change
SR with S=1 gives ______.
Answer: set
SR with R=1 gives ______.
Answer: reset
T FF can be made from ______ FF.
Answer: JK
D FF removes ______ input condition.
Answer: invalid
Flip-flop has ______ stable states.
Answer: two
State transitions are shown using ______.
Answer: arrows
States are shown using ______ in diagram.
Answer: circles
Sequential logic is ______ dependent.
Answer: time
Flip-flop is a ______ circuit.
Answer: sequential
SR latch is simplest ______ device.
Answer: memory
Clocked SR is called ______ SR.
Answer: gated
Toggle means ______ state.
Answer: change
Present state is also called ______ state.
Answer: current
Next state is ______ state.
Answer: future
Excitation table is reverse of ______ table.
Answer: state
D FF has ______ data input.
Answer: single
JK stands for ______ and ______.
Answer: J, K
Flip-flop output changes only on ______ trigger.
Answer: clock
T FF output when T=0 is ______.
Answer: same
Sequential circuits are also called ______ circuits.
Answer: memory
Flip-flop is a ______ multivibrator.
Answer: bistable
State table rows represent ______.
Answer: states
State diagram helps in ______ of system.
Answer: design
One flip-flop stores ______ bit of information.
Answer: one

===============================================================

Topics :- Registers and Counters

PART–1: MCQs (Registers & Counters)

1. A register is primarily used to store:
A) Instructions only
B) Data temporarily
C) Permanent files
D) Programs
Answer: B

2. Registers are located in:
A) Hard disk
B) Main memory
C) CPU
D) Cache only
Answer: C

3. Which register holds the address of next instruction?
A) IR
B) MAR
C) PC
D) ACC
Answer: C

4. PC stands for:
A) Program Counter
B) Process Code
C) Program Control
D) Primary Counter
Answer: A

5. IR register stores:
A) Data
B) Instruction
C) Address
D) Result
Answer: B

6. MAR stands for:
A) Memory Address Register
B) Memory Access Register
C) Main Address Register
D) Machine Address Register
Answer: A

7. MDR is used to hold:
A) Instruction only
B) Address only
C) Data from memory
D) Opcode
Answer: C

8. Accumulator is used for:
A) Storing instructions
B) Arithmetic operations
C) Address storage
D) Control signals
Answer: B

9. Registers are faster than:
A) Cache
B) RAM
C) CPU
D) ALU
Answer: B

10. Register size is measured in:
A) Bytes
B) Words
C) Bits
D) KB
Answer: C

11. General purpose registers are used for:
A) Fixed function only
B) Temporary storage
C) Permanent storage
D) Output only
Answer: B

12. Special purpose registers include:
A) GPR
B) Index register
C) Flags register
D) Both B and C
Answer: D

13. Flag register stores:
A) Instructions
B) Status bits
C) Addresses
D) Programs
Answer: B

14. Zero flag is set when result is:
A) Negative
B) Zero
C) Positive
D) Large
Answer: B

15. Carry flag indicates:
A) Borrow
B) Overflow bit
C) Extra carry
D) Sign
Answer: C

16. A counter is a:
A) Storage device
B) Sequential circuit
C) Combinational circuit
D) Memory chip
Answer: B

17. Counter counts:
A) Voltage
B) Clock pulses
C) Programs
D) Files
Answer: B

18. Counter is made using:
A) Gates
B) Flip-flops
C) Registers
D) Multiplexers
Answer: B

19. Number of flip-flops in a mod-16 counter:
A) 2
B) 3
C) 4
D) 8
Answer: C

20. Modulus of counter means:
A) Max count
B) Min count
C) Clock rate
D) Memory size
Answer: A

21. Up counter counts:
A) Downward
B) Random
C) Increasing
D) Decreasing
Answer: C

22. Down counter counts:
A) Increasing
B) Decreasing
C) Random
D) Binary only
Answer: B

23. Ripple counter is also called:
A) Asynchronous counter
B) Synchronous counter
C) Static counter
D) Linear counter
Answer: A

24. In synchronous counter, flip-flops are triggered by:
A) Different clocks
B) Same clock
C) No clock
D) Random pulses
Answer: B

25. Ring counter is made using:
A) Shift register
B) ALU
C) RAM
D) Decoder
Answer: A

26. Johnson counter is also called:
A) Twisted ring counter
B) Up counter
C) Down counter
D) Ripple counter
Answer: A

27. A 3-bit counter has maximum count:
A) 3
B) 6
C) 7
D) 8
Answer: D

28. Binary counter counts in:
A) Decimal
B) Octal
C) Binary
D) Hex
Answer: C

29. Preset input is used to:
A) Clear counter
B) Load value
C) Increment
D) Stop clock
Answer: B

30. Clear input makes counter value:
A) Max
B) One
C) Zero
D) Random
Answer: C

31. Which register holds current instruction?
A) IR
B) PC
C) MAR
D) MDR
Answer: A

32. Which register interacts with memory address?
A) MAR
B) IR
C) ACC
D) PC
Answer: A

33. Stack Pointer register is used for:
A) Arithmetic
B) Stack tracking
C) I/O
D) Timing
Answer: B

34. Index register is used in:
A) Indexed addressing
B) Direct addressing
C) Immediate addressing
D) None
Answer: A

35. Counter circuit is an example of:
A) Sequential logic
B) Combinational logic
C) Analog circuit
D) Memory cell
Answer: A

36. Flip-flop stores:
A) One bit
B) Two bits
C) Four bits
D) One byte
Answer: A

37. A register with n flip-flops stores:
A) n bits
B) 2n bits
C) n bytes
D) 4n bits
Answer: A

38. Control register is used for:
A) Data
B) Control signals
C) Address
D) Results
Answer: B

39. Counter output sequence depends on:
A) Clock
B) Memory
C) Compiler
D) Program
Answer: A

40. Synchronous counters are:
A) Slower
B) Faster
C) Same
D) Random
Answer: B

41. Asynchronous counters suffer from:
A) Propagation delay
B) No output
C) Noise only
D) Heat
Answer: A

42. Mod-10 counter is also called:
A) Binary counter
B) Decade counter
C) Ring counter
D) Up counter
Answer: B

43. Register transfer language is abbreviated as:
A) RTL
B) RML
C) RCL
D) RPL
Answer: A

44. RTL describes:
A) Hardware structure
B) Register operations
C) Software code
D) Compiler rules
Answer: B

45. Parallel load register loads data:
A) Bit by bit
B) All bits at once
C) Randomly
D) Serially
Answer: B

46. Shift register shifts data:
A) Left/Right
B) Up/Down
C) Circular only
D) None
Answer: A

47. Counter that counts both directions:
A) Ripple
B) Up-down counter
C) Ring
D) Johnson
Answer: B

48. Counter reset signal makes output:
A) Max
B) Zero
C) One
D) Toggle
Answer: B

49. Status register is also called:
A) Flag register
B) MAR
C) IR
D) PC
Answer: A

50. Fastest storage in computer is:
A) Register
B) RAM
C) Cache
D) Disk
Answer: A

PART–2: Fill in the Blanks (with Answers)

Registers are located inside the CPU
PC stands for Program Counter
IR stores the current instruction
MAR holds the memory address
MDR holds memory data
Accumulator is used for arithmetic operations
Registers are made of flip-flops
One flip-flop stores 1 bit
Flag register stores status bits
Zero flag indicates result is zero
Counter counts clock pulses
Counter is a sequential circuit
Ripple counter is asynchronous
Synchronous counter uses common clock
Modulus means maximum count
Mod-10 counter is decade counter
Ring counter uses shift register
Johnson counter is twisted ring counter
Up counter counts increasing
Down counter counts decreasing
Up-down counter counts in both directions
Clear input resets counter to zero
Preset input loads a value
Register size is measured in bits
Stack pointer tracks stack location
Index register supports indexed addressing
Status register is also called flag register
RTL stands for Register Transfer Language
Parallel load loads all bits at once
Shift register shifts data
Registers are faster than RAM
General purpose registers store temporary data
Special purpose registers have fixed roles
Counter output changes with clock
Binary counter counts in binary
A 4-bit counter counts up to 16 states
Asynchronous counters have propagation delay
Synchronous counters are faster
Control register stores control signals
Instruction register holds opcode
MAR connects to address bus
MDR connects to data bus
Register transfer is denoted by ←
Flip-flops are bistable devices
Register group is called register file
Counter is built using flip-flops
Mod-8 counter needs 3 flip-flops
Highest speed memory is register
Sequence of counter is called counting sequence
Reset signal makes output 0

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DR. PANKAJ DADHICH

Computer Organizations- Question Paper- 3